1. Field of Invention
The present invention relates to a vertical routing structure. More particularly, the present invention relates to a vertical routing structure inside a substrate.
2. Description of Related Art
Flip chip bonding technology is a packaging technique that attaches a die to a carrier. To form a flip chip package, bumps are formed on an area array of die pads on a die and then the die is flipped over so that the bumps on the die can join up with bonding pads on the surface of the carrier both electrically and mechanically. Because flip chip bonding technology can be applied to form a chip package with a high pin count, a small package area and a short signal transmission pathway, it is one of the most popular chip packaging techniques. Note that a properly design substrate has the capacity to increase overall density of contacts and reduce size of circuits. Hence, substrate is the most commonly used carrier in a flip chip package.
FIG. 1A is a schematic cross-sectional view showing a portion of a conventional substrate having a total of six circuit layers therein altogether. As shown in FIG. 1A, the substrate 100 uses a dielectric core layer 110c as a base. Through mechanical drilling, a plurality of through holes 112a is formed in the dielectric core layer 110c. An electroplating process is carried out to coat a layer of conductive material over the interior wall of the through holes 112a and the top and bottom surface of the dielectric core layer 110c. Thereafter, resinous material is injected into the through holes 112a to consolidate the substrate 100 and form a plurality of through vias 130a (only one is shown). To simplify the description, only the process for forming the layers above the dielectric core layer 110c is discussed below.
After forming the through vias 130a, a non-patterned circuit layer 120c is formed over the circuit layer 120d. The circuit layer 120c and the circuit layer 120d are patterned to form a circuit on the top surface of the dielectric core layer 110c. Thereafter, a dielectric layer 110b is formed over the circuit layer 120c. The dielectric layer 110b is patterned to form a plurality of openings 112b (only one is shown) by conducting a photolithographic process. Conductive material is deposited into the openings 112b to form conductive vias 130b. Another non-patterned circuit layer 120b is formed over the dielectric layer 110b and then the circuit layer 120b is patterned to form bonding pads 124b thereon. The aforementioned steps for fabricating the dielectric layer 110b and the circuit layer 120b are repeated to form a dielectric layer 110a and a circuit layer 120a sequentially over the circuit layer 120b. In addition, the aforementioned steps can be repeated to form a circuit layer 120f, a dielectric layer 110d, a circuit layer 120g, a dielectric layer 110e and a circuit layer 120h sequentially over the bottom surface of the dielectric core layer 110c. Hence, a substrate 100 having a total of six circuit layers therein is built. In the six-layered substrate structure 100, the circuit layer 120c and the circuit layer 120d can be regarded as one circuit layer. Similarly, the circuit layer 120e and the circuit layer 120f can also be regarded as one circuit layer.
FIG. 1B is a top view of a portion of the substrate structure shown in FIG. 1A and FIG. 1C is a portion of the sectional view along line I—I of FIG. 1B. As shown in FIG. 1A, the circuit layer 120a and the circuit layer 120b are electrically connected through the conductive via 130b. The top end of the conductive via 130b connects to the bonding pad 124a provided by the circuit layer 120a and the bottom end of the conductive via 130b connects to the bonding pad 124b provided by the circuit layer 120b. In addition, aside from these bonding pads 124, the circuit layers 120 also provides a plurality of trace lines 122 running between the bonding pads 124.
As shown in FIGS. 1B and 1C, the opening 112b in the dielectric layer 110a is formed in a photolithographic process. Hence, the smallest diameter at the bottom end of the opening 112b is only about 60 μm. Furthermore, an alignment tolerance of about 30 μm is normally provided between the opening 112b and the bonding pad 124b during a photolithographic process of the dielectric layer 110a. Therefore, the smallest diameter of the bonding pad 124b is about 120 μm (that is, (60+30×2)μm). Additionally, to prevent possible short-circuit between the bonding pad 124 and its neighboring trace line 122 when the circuit layer 120a is patterned (normally by conducting photolithographic and etching processes), a pitch P1 not smaller than 50 μm must be set aside between the two.
With the circuit layer 120a and the circuit layer 120b designed to be electrically connected through a conductive via 130b, if the bottom end of the conductive via 120b has an outer diameter of 60 μm and the bonding pad 124b at the bottom end of the conductive via 130b has an alignment tolerance of 30 μm, an alignment tolerance of about 50 μm must be provided between the bonding pad 124b and the circuit layer 120b. In other words, the substrate 100 in FIG. 1A must provide a circular area in the horizontal plane with a diameter in excess of 220 μm (that is, 60+30×2+50×2 μm). However, as the number of signal transmission path increases, the number of conductive vias 130b and the horizontal area on the substrate 100 needed to accommodate the conductive vias 130b must be increased accordingly. Furthermore, the through holes 112a in the dielectric core layer 110c are formed by a mechanical drilling process so that the smallest diameter D1 of the through hole 112a is only about 100 μm. As a result, the smallest outer diameter of the through via 130a (including the coated layer) is about 160 μm and hence precludes any further optimization of substrate area. In other words, bringing the vias closer together to increase routing density is difficult for a substrate with conventional conductive vias or embedded vias (130b) and through vias (130a) therein.